1. Technical Field
The present invention relates to a synchronous semiconductor memory device, and more particularly, to a delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of a load connected to a data pin of the synchronous semiconductor memory device, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device.
2. Discussion of the Related Art
Generally, synchronous semiconductor memory devices such as double data rate synchronous DRAMs (DDR SDRAMs) use an internal clock signal synchronized with an external clock signal to write or read data. More specifically, the DDR SDRAMs write or read data every half period of the internal clock signal. The internal clock signal is generated by using a delay locked loop (DLL) circuit.
FIG. 1 is a block diagram illustrating a conventional synchronous semiconductor memory device 100 including a DLL circuit 110 and an output driver 130.
The DLL circuit 110 includes a variable delay circuit 111, a phase detector 113, a control circuit 115, and a replica output driver 117.
The replica output driver 117, which is included in a feedback loop of the DLL circuit 110, replicates a delay time of an internal clock signal ICLK that is delayed through the output driver 130. The delay time of the internal clock signal ICLK is caused by a load LD (internal or external) connected a data pin DQ. The data pin DQ is connected to an output terminal of the output driver 130. The load LD may be a capacitor or a memory system including a single rank dual in-line memory module (DIMM). The magnitude of the load LD when it is a memory system including a single rank DIMM is relatively small.
As shown in FIG. 1, the phase detector 113 detects a phase difference between a delayed version of the internal clock signal ICLK_D delayed through the replica output driver 117 and an external clock signal ECLK. The control circuit 115 generates a control signal to control the amount of delay through the variable delay circuit 111 in response to an output signal from the phase detector 113. The variable delay circuit 111 delays the external clock signal ECLK to generate the internal clock signal ICLK synchronized with the external clock signal ECLK in response to the control signal from the control circuit 115.
The output driver 130 synchronizes data DATA output from a memory cell (not shown) of the synchronous semiconductor memory device 100 with the internal clock signal ICLK and outputs the data DATA to the data pin DQ. The output driver 130 is also called an output buffer.
FIG. 2 illustrates an example of the load LD connected to the data pin DQ. In particular, a memory system 200 is illustrated as the load LD.
Referring to FIG. 2, the memory system 200 includes a memory controller 210, a bus channel 220, memory modules 230 and 240, and memory slots 250 and 260.
The memory controller 210 controls data to be input to or output from the memory modules 230 and 240 through the bus channel 220. The memory controller 210 is also called a chip set.
The bus channel 220 includes a data bus and a control bus. The control bus transmits a control signal such as a clock signal or an address signal to control data transmitted through the data bus.
Each of the memory modules 230 and 240 is installed (or inserted) in corresponding memory slots 250 and 260 so that they may be connected to the memory controller 210 through the bus channel 220. Each of the memory modules 230 and 240 is a DIMM with two ranks R0 and R1, or R2 and R3. Each of the ranks R0, R1, R2 and R3 may include a plurality of synchronous semiconductor memory devices such as the synchronous semiconductor memory device 100 illustrated in FIG. 1. The ranks R0 and R1, or R2 and R3 may be configured to form a single rank DIMM in which a single semiconductor memory device is connected to a single data bus or a double rank DIMM in which two semiconductor memory devices are connected to a single data bus.
Referring back to FIG. 1, the delay time of the internal clock signal ICLK generated by the output driver 130 is changed according to the magnitude of the load LD (or the number of ranks) connected to the data pin DQ. In other words, when the load LD is a memory system including a single rank DIMM, which is considered to be a relatively light load, the delay time of the internal clock signal ICLK is small, but when the load LD is a memory system including a double rank DIMM, which is considered to be a relatively heavy load, the delay time of the internal clock signal ICLK is large.
In addition, the delay time of the internal clock signal ICLK that is delayed through the replica output driver 117 is set on the basis of a memory system including a single rank DIMM. Therefore, if the load LD is a memory system including a double rank DIMM, a clock access time tAC margin of the synchronous semiconductor memory device 100 is decreased. In other words, an interval between a reference edge of the external clock signal ECLK and the output of data may be decreased. Therefore, the output driver 130 may not output valid data in synchronization with the external clock signal ECLK. Further, as an operating frequency of the synchronous semiconductor memory device 100 increases, the tAC margin may additionally decrease.
A need therefore exists for a synchronous semiconductor memory device including a DLL circuit that is capable of preventing a tAC margin from decreasing so that valid data may be output.